Self-assembled nanostructures, in particular semiconductor nanowires, which have been researched intensively for a few years, could soon be used as elementary components in computer chips. This is due to the significantly superior electron mobility in group III/V semiconductor nanowires compared with the conventional silicon CMOS technology. Moreover, there is the possibility of optoelectronic functionality, as well as the use of new, electrically controllable magnetic functionality in the field of spintronics, as well as the use, sought after by many working groups, of nanowires in the field of quantum computing. Applications in the field of spintronics are of particular importance, since group III/V semiconductor nanowires in addition often make it possible to also control the spin, i.e. the intrinsic angular momentum, of the electrons in a transistor, in addition to the electronic property of the charge.
In the field of spintronics, making use of nanowires leads to particular challenges, since electrical contacting using magnetizable electrodes requires the nanostructures to be planarized in advance (FIG. 1).
Thin metal layers, which have been used hitherto for electrically contacting the nanowires, may be interrupted due to the geometry (by shadowing effects during the directed deposition) (FIG. 1a). In ferromagnetic materials, which are used for electrically injecting spin-polarized currents, undesired and inhomogeneous alignment of the local magnetization may occur (FIG. 1b). Domain formation of this kind renders the component unusable for applications in the field of spintronics.
Spin-on oxide (e.g. hydrogen silsesquioxane by Dow Corning®), also referred to in the following as HSQ, has already been used multiple times in literature for planarizing nanowires (FIG. 2). After being spun on, the HSQ layer was removed again by means of reactive ion etching until the upper face of the nanowire was again exposed [1-3].
The method mentioned above has the advantage that individual nanowires can be planarized by means of embedding in an oxide layer (FIG. 2). However, the etching time must be precisely adjusted for each nanowire, depending on the diameter of the nanowire and the local oxide layer thickness, and must be laboriously monitored, by means of scanning force microscopy, between a plurality of etching steps of the etching progress. As a result, in a sample, only nanostructures/nanowires having an identical diameter can be optimally planarized at the same time. In addition, the reactive ion etching/plasma etching may, in some circumstances, negatively influence the nanostructures/nanowires (in particular the surface properties thereof).
Moreover, there are significant process-related difficulties with regard to the vertical integration of horizontal nanowires or of nanowire networks in application. CMP (chemical mechanical planarization) is a central aspect of computer chip production and is of decisive importance for the vertical integration, which is conventional in modern computer chips, since a plurality of layers of conductor tracks, transistors or logic components are always arranged on top of one another with a degree of precision in nanometers. Since CMP cannot be used for nanowires and other nanostructures or affects the structural integrity thereof, an iterable method is required which can apply a plurality of nanowire layers on top of one another without CMP or etching steps, which layers can be connected by vertical feedthroughs (known as vias-vertical interconnect access) (FIG. 11).
HSQ has already been used for layer transfer [4, 5]. The method implements HSQ in order to connect two wafers by means of wafer bonding. In this case, the HSQ does not serve to transfer or planarize nanostructures, but instead merely allows a connection between a silicon wafer and a GaN layer. Moreover, the initial substrate is not removed by dissolving a contact layer (e.g. of PMMA) in a solvent, but instead the entire transfer wafer (i.e. the initial substrate) is removed by means of reactive ion etching.
Sheng et al. [6] have proposed a method for transferring nanowires. The aim in this case is to conduct an electrical current laterally, instead of axially, through the ZnO nanowires. For this purpose, the nanowire is aluminized, and the transfer wafer comprising the aluminum layer is adhesively bonded to another Si wafer using an adhesive. Since the bond between aluminum and silicon is only weak, the adhesively bonded wafer comprising the aluminum layer and the nanowires embedded therein can be removed by means of mechanical shearing forces. The nanowires are in the aluminum layer, and said layer is planar on the surface since it originally formed the junction with the silicon. This method, too, results in planarization of nanowires. Here, however, the nanowire is embedded in a metal electrode. This electrically short-circuits the nanowire along the growth axis thereof, and thus does not allow for an application within the meaning of the present invention.
In particular, vertical integration of planar, integrated circuits consisting of nanostructures/nanowires is not possible in the method mentioned above.